1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
Fabrication of semiconductor memory cannot completely be exempt from failure in the memory cell. It is therefore general practice to configure the circuit in a redundant manner in order to rescue the semiconductor memory containing defective cells.
This configuration allows even a semiconductor memory having defective memory cells to normally operate, by replacing fault bits with redundant bits. The replacement is effected using a fuse as described in Japanese Laid-Open Patent Publication No. 6-140510. That is, interconnection is replaced by blowing the fuse.
FIG. 8 is a circuit drawing showing a fuse peripheral circuit described in the patent publication in the above. In this configuration, a fuse 100 is blown by bringing a terminal 101 to a high level to thereby turn an NFET transistor 102 on. This allows current to flow through the fuse 100, so that the fuse 100 blows. Whether the fuse 100 has been blown or not can be judged by raising the level of a terminal 103 to high, to thereby bring the node 104 down to low. Next, the terminal 103 is switched to low, to thereby turn a PFET transistor 105 on. In this case, the node 104 remains low if the fuse 100 has been blown. On the other hand, if the fuse has not been blown, both of the fuse 100 and the transistor 105 electrically conduct to thereby bring the node 104 up to high. It is therefore made possible to judge whether the fuse 100 has been blown or not based on the potential appears at the node 104. The potential is stored in a latch circuit as a signal indicating result of judgment on whether the fuse 100 has been blown or not.